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| -rw-r--r-- | README.md | 16 |
1 files changed, 10 insertions, 6 deletions
@@ -10,8 +10,8 @@ is to allow a drop-in replacement in Cryptech designs. ## Status ## -Second round of optimizations done. Core similates correctly. Core has -been implemented in FPGA, but not functionally tested in real HW. +Second round of optimizations done. The core has been implemented in +FPGA and tested in real HW. ## Introduction ## @@ -36,12 +36,16 @@ the total number of S-boxes is 40. ## Performance comparison Number of cycles for the old Cryptech AES core: -- AES-128 Encipher one block with key expansion: 57 -- AES-256 Decipher one block with key expansion: 77 +- AES-128 Encipher one block: 57 +- AES-256 Decipher one block: 77 Number of cycles for the Cryptech AES speed core: -- AES-128 Encipher one block with key expansion: 16 -- AES-255 Decipher one block with key expansion: 20 +- AES-128 Encipher one block: 16 +- AES-255 Decipher one block: 20 + +Note that these latency numbers are after key expansion. The given key +must be expanded byt asserting the init control bit and wait for ready +to be asserted. Key expansion takes about 10 to 14 cycles. ## Implementation comparison |