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| author | Joachim StroĢmbergson <joachim@secworks.se> | 2018-09-27 15:08:19 +0200 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2018-09-27 15:08:19 +0200 |
| commit | 9af80907f9d1913cd8cb200eabe5e99cc65021a4 (patch) | |
| tree | afeb4ec1491932a0f9e42b8efde28f8c85e887a8 /src/rtl/aes_core.v | |
| parent | c1225cb6c9843e91f3b3dfee294fc1f9309e8212 (diff) | |
Added missing reset of registers. This fixes CT-01-001 FPGA.
Diffstat (limited to 'src/rtl/aes_core.v')
0 files changed, 0 insertions, 0 deletions