Cryptech Project

Name	Description	Idle
user/shatov/ecdsa256	Scalar base point multiplier for ECDSA curve P-256	6 years
user/shatov/modexp_fpga_model	Reference model was written to help debug Verilog code	7 years
user/sra/openssl-engine	Examples using OpenSSL over Cryptech HSM via PKCS 11 and OpenSSL ENGINE API	7 years
user/shatov/ecdsa384	Scalar base point multiplier for ECDSA curve P-384	7 years
user/ft/stm32-avalanche-noise	STM32 avalanche noise entropy source	7 years
user/ft/bootstrap	Bootstrap scripts used with the Alpha board	8 years
sw/tamper	Cryptech prototype tamper protection software	8 years
user/paul/libcli	libcli emulates a cisco style telnet command-line interface	8 years
doc/design	Design documentation	8 years
user/jakob/tamper	Cryptech tamper detection	8 years
user/ft/tamper	Cryptech tamper detection	8 years
user/jakob/benchmark	Cryptech Benchmark	8 years
releng/novena	Release engineering for early Cryptech code on Novena	8 years
user/ln5/tamper	Cryptech tamper detection	8 years
sw/thirdparty/sqlite3	(Old) SQLite3 port once used by Cryptech PKCS #11	8 years
sw/cryptlib	(Old) port of cryptlib to Novena	8 years
user/ft/libcli	libcli emulates a cisco style telnet command-line interface	8 years
sw/thirdparty/ekermit	(Old) EKermit library once considered for HSM firmware uploads	8 years
user/shatov/ModExpA7	Unnamed repository; edit this file 'description' to name the repository.	8 years
user/shatov/stm32_sdram	Unnamed repository; edit this file 'description' to name the repository.	8 years
user/shatov/stm32_n25q128	Unnamed repository; edit this file 'description' to name the repository.	8 years
core/util/mkmif	Master Key Memory Interface	8 years
user/ft/stm32-dev-bridge	Unnamed repository; edit this file 'description' to name the repository.	8 years
core/platform/terasic_c5g	Platform-specific files for the TerasIC C5G development board	8 years
core/math/modexp	Modular exponentiation core	8 years
core/comm/uart	A Universal asynchronous receiver/transmitter (UART) implemented in Verilog	8 years
core/comm/i2c	An I2C slave implemented in Verilog	8 years
core/comm/eim	Verilog implementation of EIM interface used to connect FPGA cores to Freescale ...	8 years
core/comm/coretest	Test platform for the Cryptech Open HSM project	8 years
core/math/modexps6	Unnamed repository; edit this file 'description' to name the repository.	8 years
user/shatov/novena-fmc-arbiter	FMC interface arbiter for Novena's on-board Spartan-6 FPGA	9 years
user/shatov/fmc-test	Demo program for stm32-dev-bridge board to test FMC arbiter in Novena's on-board...	9 years
test/external_avalanche_entropy	External Avalanche Entropy	9 years
doc/presentations	Presentations about the Cryptech project and the Cryptech HSM design	9 years
user/shatov/gost/streebog_tester	Unnamed repository; edit this file 'description' to name the repository.	9 years
user/shatov/gost/streebog	Unnamed repository; edit this file 'description' to name the repository.	9 years
test/novena_i2c_simple	Coretest system for Novena PVT1, over I2C, with simplified user interface	9 years
test/coretest_test_core	Coretest module combined with the test_core as a test module	9 years
test/test_core	Simple test core with 32-bit memory-like interface and debug port	9 years
core/rng/vndecorrelator	Verilog implementation of a von Neumann decorrelator	9 years
test/novena_base	Cryptech Novena FPGA baseline	9 years
test/novena_trng	Experimental HW system for the Novena platform	9 years
test/novena_entropy	Experimental HW system for the Novena platform	9 years
test/coretest_bp_entropy	Coretest System for testing FPGA based entropy source developed by Bernd Paysan	10 years
test/coretest_fpga_entropy	Coretest system for testing FPGA based entropy source	10 years
test/fpga_entropy	Test implementation of FPGA-internal entropy source	10 years
user/sra/pelican	Convert trac.cryptech.is to markdown with pelican